The present invention relates to a semiconductor apparatus in which a field-effect transistor (FET) is disposed and to a method of manufacturing the same. More particularly, it relates to a method of lowering the resistance of an impurity diffusion layer in the FET.
With the increasing miniaturization of a large-scale semiconductor integrated circuit in recent years, a MISFET has been reduced in size by lowering the resistances of its impurity diffusion layer and gate interconnection. To lower the resistance of an impurity diffusion layer, there has been developed "salicide" technology for actual use, which is a method wherein a metal with high melting point such as Ti is deposited on the impurity diffusion layer in a silicon substrate and then the vicinity of the Si--Ti interface is silicidized through the mutual diffusion of Si and Ti between the silicon substrate and the resulting Ti film, thereby lowering the resistance value of the impurity diffusion layer. On the other hand, there has been introduced a method wherein tungsten is buried in a contact hole by selective CVD or blanket tungsten is used to fill up the contact hole, since the aspect ratio of the contact hole has been increased in order to minimize the contact area between the interconnection and silicon.
There has also been proposed a method, which is a combination of the above two technologies, in "A NOVEL DOUBLE-SELF-ALIGNED TiSi.sub.2 /TiN CONTACT WITH SELECTIVE CVD W PLUG FOR SUBMICRON DEVICE AND INTERCONNECT APPLICATIONS (IEEE. VLSI Symp 5--5 p.41, 1991)" by Martin S. Wang et al.
Below, the composite salicide method disclosed in the above document will be described with reference to FIGS. 18(a) to 18(f), which illustrate the transition of the cross sectional structure of a silicon substrate during the process of manufacturing a semiconductor apparatus.
FIG. 18(a) shows a MOS transistor of LDD structure that has been formed previously. In the drawing, 1 designates a silicon substrate, 2 designates an isolation formed by a LOCOS method, 3 designates: a gate oxide film, 4 designates a polysilicon electrode, 5 designates a side wall, and 6 designates an impurity diffusion layer (the impurity diffusion layer includes a low-concentration source/drain 6a and a high-concentration source/drain 6b). The manufacturing method is identical with a conventional method of manufacturing a CMOS device, up to the stage shown in FIG. 18(a). Moreover, the doping with As, P, and B and the subsequent thermal treatment have been conducted in accordance with the characteristics of a p-channel MOS transistor. Next, as shown in FIG. 18(b), a Ti thin film 30 for a salicide is deposited by sputtering, followed by annealing for silicidization as shown in FIG. 18(c). After that, the titanium on the oxide film is removed by wet etching so as to implant N.sub.2. Subsequently, TiSi.sub.x (silicidized titanium layer) 30 is formed only on the impurity diffusion layers 6 and gate polysilicon 4. After a BPSG film 10 weas deposited, a contact hole 11 is formed in a desired position of the BPSG film 10 by photolithography and by dry etching (using a gas containing CHF.sub.2 +O.sub.2 as its main component), as shown in FIG. 18(d). Next, as shown in FIG. 18(e), a W (tungsten) plug 12 is deposited by selective CVD. Then, after depositing a film consisting of TiN/AlSiCu/Ti by sputtering, as shown in FIG. 18(f), the resulting film is patterned to form a metal interconnection 13. The above process provides a semiconductor apparatus having the MOS transistor with the salicide structure and the W plug formed by selective CVD.
However, the conventional semiconductor apparatus with the structure described above has the following disadvantages:
(1) Although the formation of a silicide film 7b requires the reaction between the metal with high melting point and the underlying silicon, if the impurity diffusion layer 6 is shallow, it becomes difficult to form a junction between the metal with high melting point and silicon. However, since a future device requires the formation of an impurity diffusion layer as shallow as possible. it becomes difficult to form an effective junction, so that the salicide technology is not necessarily compatible with a future device. PA1 (2) Since the silicide layer shows poor immunity to a gas containing CF as its main component in etching for forming a contact hole, defects such as a pin hole are easily caused, which may incur an increase in the resistance of the impurity diffusion layer. PA1 (3) In a transistor with a shallow junction formed between the metal with high melting point and silicon, over-etching for surely forming each contact hole cannot be performed satisfactorily in etching for forming a contact hole in the shallow junction therebetween. Consequently, the reliability of an interconnection may be impaired. PA1 (4) A thermal treatment at 650.degree. C. or a higher temperature is required in order to lower the resistance of the silicide layer. Consequently, the electrical characteristics of the transistor may be impaired. PA1 (5) The silicide layer hardly serves as a satisfactory barrier metal layer in forming the W plug by selective CVD, so that its manufacturing conditions for preventing junction leakage become more stringent. PA1 (6) With the structure shown in FIG. 18(f), the degree of planarization of the base underlying the BPSG film 10 is not satisfactory.